It has been proposed that solid state Random Access Memories (RAM's) be used as replacements for direct access storage devices (e.g. disk drives). To assure non-volatility for such memories, it has further been proposed that low powered DRAMs, with battery backup be employed. The battery backup provides the required non-volatility of the stored data in the event of a power failure.
As is known, DRAMs require a periodic refresh to maintain the data states stored in the cells. Presently, such refresh cycles are programmed to occur at intervals of much less than a second. While such a short interval between refresh cycles readily maintains the stored data in a DRAM, it places a substantial duty cycle on a backup battery and reduces the down-time capability of the memory. The governing factor which determines the interval between refresh cycles is the time it takes for the "most leaky", but operable cell to dissipate its stored charge to a level that can cause data loss. In the prior art, a variety of solutions have been proposed for coping with either the loss of data in DRAM cells arising from a loss of charge, or to the inoperability of such cells. In U.S. Pat. No. 4,610,003 to Natori, a DRAM cell is shown wherein charge leakage control is implemented by changing the turn-off voltage applied to the gate of a cell's transistor. The voltage change increases the insulation between the transistor's source and drain electrodes and prevents discharge of the storage capacitor. In U.S. Pat. No. 4,449,205 to Hoffman, a DRAM cell is shown which includes a non-volatile backup store. In Japanese Patent 61-214297 to Sawata, a leak monitor circuit is employed with a DRAM cell and is used to set an optimum refresh operating allowance so as to assure continued viable data storage in the cell.
In order to determine the viability of individual cells within a DRAM, the prior art has disclosed various techniques for testing such cells. Two of such techniques are disclosed by Gutmann et al., IBM Technical Disclosure Bulletin, Vol. 28, No. 5, October 1985 pages 2172-2173 and by Kindseth, IBM Technical Disclosure Bulletin Vol. 25, No. 4, September 1982 pages 2032-2035. Gutmann et al. indicate that the refresh capability of a DRAM is conventionally tested by first writing data to the memory and then waiting for a period of time before reading it back to see if it is accurately reproduced. In this instance, Gutmann et al suggest that the row address strobe signal be used to eliminate the need for a long waiting period during the test. Kindseth on the other hand, suggests modifying the ongoing refresh cycle of a DRAM to apply the stored data to error correcting circuitry. In other words, the error correction and store operations both occur during the refresh cycle.
In lieu of giving up valuable chip real estate for charge enhancing circuity for every cell or for continuous testing of such cell arrays, the prior art teaches the use of redundant storage cells to replace defective DRAM cells. Characteristically, such DRAMS include a programmable read only memory (PROM) which contains the addresses of the defective memory cells. The contents of the PROM are inserted at the time the DRAM is subjected to "final test" in the manufacturing operation and identifies those cells which are defective and are to be replaced by the redundant cells.
When an address is received for one of the defective memory cells, the address is compared with one of the addresses stored in the PROM and if a match is found, the decoder feeding the regular memory cell array is inhibited and a decoder feeding the redundant array is enabled. Such operation is shown in U.S. Pat. No. 4,757,474 to Fukushi et al., however, they employ a multilevel selection circuit for determining which memory addresses are to go to the redundant cells decoder. The selection circuit examines the most significant and least significant address bits to make the determination. DRAM's employing redundant cells also can be found in U.S. Pat. Nos. 4,745,582 to Fukushi et al., 4,752,914 to Nakano et al., 4,783,781 to Awaya, 4,750,158 to Giebel et al., 4,748,597 to Saito et al., 4,691,301 to Anderson, 4,688,219 to Takemae, 4,630,241 to Kobayashi et al., 4,672,581 to Waller, 4,691,300 to Pelley, III et al. and 4,737,935 to Wawersig et al. In each of the above patents the concept is taught of a memory device that, upon detecting an address to a defective cell redirects such address to a redundant cell.
Accordingly, it is an object of this invention to provide a DRAM that exhibits decreased power requirements and increased intervals between refresh cycles.
It is another object of this invention to provide a DRAM which is particularly suited to perform the function of a direct access storage device.
It is still a further object of this invention to provide a low power DRAM with redundant storage cells that enable the DRAM to exhibit, non-volatile storage capabilities.